Targeting the Analog Verification Gap: State Space-based Formal Verification Approaches for Analog Circuits

Analog circuit verification lacks systematization and formalization. The major weakness of todays verification flows is their uncertainty about verification coverage. This contribution demonstrates how novel approaches can overcome this coverage problem by considering the complete analog state space for verification. An approach to model checking proves the absence or existence of errors with respect to a machinereadable property specification. By injecting particles into the continuous vector field representing the state space of analog circuits and inspecting their simulated parallel motion according to the circuit’s dynamics, another complete and therewith formal verification approach is given. The application to a circuit example shows the feasibility of both approaches.